The present invention pertains to the field of electronic design automation. More particularly, aspects of the present invention pertain to design for test (DFT) methodologies and automatic test pattern generation (ATPG) methodologies.
The rapid growth of the complexity of modern electronic circuits has forced electronic circuit designers to rely upon computer programs to assist and automate most steps of the circuit design process. Typical circuits today contain hundreds of thousands or millions of individual pieces or xe2x80x9ccells.xe2x80x9d Such a design is much too large for a circuit designer or even a team of engineers to effectively manage manually. To automate the circuit design and fabrication of integrated circuit devices, electronic design automation (EDA) systems have been developed.
An EDA system is a computer software system designers use for designing integrated circuit (IC) devices. The EDA system typically receives one or more high level behavioral descriptions of an IC device (e.g., in HDL languages like VHDL, Verilog, etc.) and translates this behavioral description into netlists of various levels of abstraction. At a higher level of abstraction, a generic netlist is typically produced based on technology independent primitives. A netlist describes the IC design and is composed of nodes (elements) and edges, e.g., connections between nodes, and can be represented using a directed cyclic graph structure having nodes which are connected to each other with signal lines. The netlist description is typically stored in computer readable media within the EDA system and processed and verified using many Well known techniques. The EDA system ultimately produces a physical device layout in mask form which can be used to directly implement structures in silicon to realize the physical IC device.
An important part of the IC design process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is known to take a netlist and add and/or replace certain memory cells with special memory cells that are designed to allow the application of test vectors to certain logic portions of the design. Another important step in the IC design process involves generating test patterns to be applied to the DFT implementations. These automatic test pattern generation (ATPG) processes analyze the various representations of the netlist designs and automatically generates test patterns therefrom.
As devices enter the sub-micron era, circuit size is increasing at a very rapid pace. With the increasing circuit size, testing is becoming more and more difficult and test data volumes are becoming unmanageable. The number of tests required to achieve high fault coverage is increasing at an even faster pace. To make the matter worse, deep sub-micron technology is challenging the existing fault models with the possibility of more failure mechanisms and more defect types. More fault models would, in turn, require more test patterns for the same fault coverage and quality level.
The increase in the number of test patterns has a significant impact on the costs associated with testing the integrated circuits. For instance, as the number of tests increases, the time required for testing the ICs will be longer. In addition, automatic testing equipment (ATE) must be constantly upgraded with more and more memory in order to cope with the increasing test data volume.
The problem with test data explosion is recognized by researchers and solutions have been presented to compress and decompress the test patterns. However, those solutions are relatively difficult to incorporate in the test tools currently available from the industry.
Therefore, what is needed is a novel method and system for testing integrated circuit designs. What is further needed is a novel method and system for generating test patterns such that test data volume and test data application time are significantly reduced.
Accordingly, the present invention provides a design for test (DFT) technique for reducing test data volume and test application time. According to the present invention, during scan conversion, non-scan memory cells of a circuit design are replaced with scan cells to form a scan chain. Significantly, the scan chain is transformed by a test synthesis tool of the present invention into dynamic scan chains with the addition of reconfiguration circuitry. The reconfiguration circuitry partitions the scan chain into multiple segments and enables each segment to be selectively xe2x80x9cbypassedxe2x80x9d (or deactivated) during test application. In this way, shorter test patterns may be used, resulting in a reduction in overall test data volume and test application time. Because the present invention offers a reduction in the test data volume to achieve the same quality of results, it is ideally suited for application to submicron integrated ciruit design.
The present invention also provides a modified ATPG technique for generating test patterns for dynamic scan chains. In furtherance of one embodiment, during ATPG processing, a test pattern for a potential fault of the design is first generated. Then, the ATPG tool of the present embodiment determines whether the specified bits of the test pattern can be applied by each segment of the dynamic scan chain(s). If all of the specified bits of a test pattern can be applied by one particular segment, the ATPG tool of the present embodiment then removes the unspecified bits that cannot be applied by that segment. As a result test data volume is advantageously reduced.
According to the present invention, if the entire scan chain is required by most of the test patterns, the initial partitioning of the dynamic scan chain(s) may be less that optimum. In that case, it may be desirable to re-partition the dynamic scan chain. In one embodiment, the partitioning may be selected by topological checks of the circuit design (e.g., circuit traversal analysis). In another embodiment, the initial partitioning may be generated randomly and subsequently refined through multiple iterations. Further, in one embodiment, the desired number of partitions within a dynamic scan chain may be parameterizable.
Embodiments of the present invention include the above and further include a computer readable memory having stored therein computer readable program code for causing a computer system to perform a method implementing design for test (DFT) circuitry in an integrated circuit design. The method of the present embodiment includes steps of: (a) receiving a netlist description of an integrated circuit design, the netlist description including a plurality of memory cells; (b) replacing the plurality of memory cells with a plurality of scan cells; (c) interconnecting the plurality of scan cells with a plurality of nets to form a scan chain; (d) selecting respective ones of the plurality of nets for insertion of reconfiguration circuitry; and (e) inserting reconfiguration circuitry at the respective nets, wherein the reconfiguration circuitry enables segments of the scan chain to be selectively bypassed during test application.